Secure Embedded Transactions (SET) works at the forefront of technology providing solutions for mobile wallet (payment, transit, access), mobile security, and UWB in consumer products ranging from smart phones to laptops.
We are seeking a new team member in San Diego to help build mobile payment and security solutions for smart phones, watches, and laptops. As a digital verification engineer, you will help us specify a test plan, verify, and validate our security SOC’s blocks. The main job role is test plan development, testbench creation, and test sequence writing in System Verilog UVM and Embedded code (C). You will also help support design reviews and validation of the block in the lab.
This cross-disciplinary role will provide the ability to directly influence a design from architecture to validation of silicon. It requires a high degree of collaboration and communication with our team members in San Diego, Germany, and France spanning multiple domains such as analog, digital, validation, and RF.
If you are looking for a job in a fast paced collaborative environment where you will see the products you work on in peoples hands everyday, we have a place for you!
• UVM test bench coding and micro-architecture
• UVM test sequence coding
• GLS simulation debug
• Embedded (C) test case coding
• Support RTL code coverage
• Hold design verification reviews
• Support validation of silicon in the lab
• Masters or Bachelor degree on EE or Computer Science
• Up to 2 years work experience, including Internships
• Hands on experience in Verilog/System Verilog
• Familiar with ASIC/SOC design flow
• Familiar with Low Power intent verification using CPF, UPF
• Scripting – PERL, Python, UNIX/LINUX
This position is available immediately, and we will also consider December graduates who can join in Q1 2022.